机读格式显示(MARC)
- 000 01189nam a2200277 a 4500
- 008 060411r20072006cc a b 000 0 eng d
- 020 __ |a 9787894854612 ( CD-ROM)
- 090 __ |a TP312VE/N316(C=2)
- 100 1_ |a Navabi, Zainalabedin.
- 245 10 |a Verilog digital system design : |b Register transfer level synthesis, testbench, and verification = Verilog数字系统设计 : RTL综合、测试平台与验证 / |c Zainalabedin Navabi著 ; 夏宇闻改编.
- 260 __ |a Beijing : |b Publishing House of Electronics Industry ; |a [S.l.] : McGraw-Hill Education (Asia) Co., |c 2007.
- 300 __ |a 17, 316 p. : |b ill. ; |c 24 cm. + |e 1 CD-ROM (4 3/4 in.)
- 504 __ |a Includes bibliographical references.
- 534 __ |a Reprint. Originally published: |c [S.l.] : McGraw-Hill Publishing Co., Inc., c2006, |b 2nd. ed. |z 0071445641.
- 650 _0 |a Verilog (Computer hardware description language)
- 650 _0 |a Electronic digital computers |x Computer-aided design.
- 700 1_ |a Xia, Yuwen |9 (夏宇闻)
- 950 __ |a JHUL |b TP312VE |c N316(C=2)