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西文图书1.Verilog digital system design : Register transfer level synthesis, testbench, and verification = Ver TP312VE/N316(C=2)
馆藏复本:3
可借复本:3 Navabi, Zainalabedin.
Publishing House of Electronics Industry ; 2007.
(0) 馆藏
馆藏复本:3
可借复本:3 Navabi, Zainalabedin.
Publishing House of Electronics Industry ; 2007.
(0) 馆藏