MARC状态：审校 文献类型：西文图书 浏览次数：31
- 题名/责任者:
- Verilog digital system design : Register transfer level synthesis, testbench, and verification = Verilog数字系统设计 ： RTL综合、测试平台与验证 / Zainalabedin Navabi著 ; 夏宇闻改编.
- 出版发行项:
- Beijing : Publishing House of Electronics Industry ; [S.l.] : McGraw-Hill Education (Asia) Co., 2007.
- ISBN:
- 9787121052415
- ISBN:
- 9787894854612 ( CD-ROM)
- 载体形态项:
- 17, 316 p. : ill. ; 24 cm. + 1 CD-ROM (4 3/4 in.)
- 丛编题名:
- 国外电子与通信教材系列.
- 个人责任者:
- Navabi, Zainalabedin.
- 附加个人名称:
- Xia, Yuwen
- 论题主题:
- Electronic digital computers-Computer-aided design.
- 中图法分类号:
- TP312VE
- 书目附注:
- Includes bibliographical references.
- 原版附注:
- Reprint. Originally published: [S.l.] : McGraw-Hill Publishing Co., Inc., c2006, 2nd. ed. 0071445641.
全部MARC细节信息>>